1. Technical Field
This disclosure relates to computer systems, and more particularly, to mechanisms for performing stores of data in a memory of a computer system.
2. Description of the Related Art
In many instruction set architectures, writes to memory are performed responsive to execution of a store instruction. Typical store instructions cause a write of data having a size (i.e. data width) equal to that of a general purpose register in that architecture (e.g., 64 bits in a 64-bit architecture). Data of this width may be written to a cache or even to memory itself responsive to execution of a store instruction. However, writing data at a data width of a general purpose register can be inefficient, particularly when executing processes which include a high number of writes to memory.
To alleviate the inefficiencies of performing a high number of writes of a limited data width, some processors may implement a structure known as a write combine buffer. A write combine buffer may receive writes from a processor core (e.g., from a store queue thereof) at the register data width. The writes may occur within a certain region of the memory space, such as a cache line. Once all the writes have been written to the cache line in the write combine buffer, the entire cache line may then be propagated to a cache memory and/or to memory.
For a single threaded processor, a single write combine buffer may be implemented. Multiple write combine buffers may be implemented for multi-threaded processors. Each write combine buffer may include storage for an address and data for each cache line that may be written thereto. For each write to a write combine buffer, all addresses stored therein may be tested in parallel, and thus the structure may be fully associative.